Alexander Kiselev is an experienced verification engineer with a strong background in block-level and subsystem verification. Currently serving as a Senior Verification Engineer at Arm since November 2021, Alexander previously held positions at SK hynix memory solutions Eastern Europe and Tecon MT, focusing on verification IP development and reusable verification components. In earlier roles as a Hardware Design Engineer at RC Module and the National Research Nuclear University MEPhI, Alexander contributed to the development of sub-components for SoC debugging systems. Alexander holds a degree in Electronics and Automation of Physical Installations from the National Research Nuclear University MEPhI, completed in 2018.
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