Devansh Rajoria is a Senior Design Engineer at Arm since April 2025, with extensive experience in memory design and compiler optimization. Previously, Devansh worked as a Senior Design Engineer at M31 Technology, leading projects on N6E HCSP and HCOP Compiler with multiple patents in progress and notable achievements in PPA optimization. Devansh's background includes a role as a subcontracted Memory Design Engineer at Broadcom, focusing on N3 Split Rail SPHD Compiler, and positions at STMicroelectronics and Zia Semiconductor, contributing to various SRAM and CMOS projects. Early career experience includes application engineering at Synopsys Inc. and an internship at 3ST Technologies. Devansh holds a Bachelor of Technology degree in Electrical, Electronics, and Communications Engineering from Guru Gobind Singh Indraprastha University.
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