Mark Dykes

Mark Dykes is a staff engineer at ARM, specializing in ASIC design with 15 years of experience in Verilog ASIC/FPGA RTL design and verification. Previously, Mark coordinated verification flows at National Semiconductor and developed test environments at Motorola and Texas Instruments, focusing on multi-processor SOCs and cache coherency. Mark's expertise includes the use of tools like Cadence, Synopsys, VCS, and Specman, along with programming in C/C++, Perl, and Python. Mark has been instrumental in developing verification tools and methodologies that have been adopted widely across the industry.