Nikhil Reddy

Nikhil Reddy is a Senior Verification Engineer at Arm since July 2018, with prior experience at Synopsys as an ASIC Design Engineer from August 2015 to July 2018, where responsibilities included developing test plans for Real Time Trace in ARC processors and performing verification using UVM. Nikhil's earlier experience includes a role as an ASIC Digital Design Engineer II, focusing on reversible gates at PESIT while completing a Master’s Degree in Electronics and Communication from 2013 to 2015, and a position as ASE-T at Tata Consultancy Services, contributing as a front-end Java developer and network administrator from 2012 to September 2013. Nikhil holds a Diploma in Design and Verification using System Verilog and UVM from RV-VLSI and an Engineer's Degree in Electrical, Electronics, and Communications Engineering from Sri Siddhartha Institute of Technology.