Sreejith Sudhakaran

Sreejith Sudhakaran is a Principal Engineer in Design Verification at ARM, where they currently apply their extensive knowledge in hardware languages including System Verilog and VHDL. With a background as a Module Leader at Wipro Technologies from 2006 to 2009, Sreejith led teams in the design and verification of SoCs and IPs, achieving Silicon success on the first attempt. Prior to that, they served as a Research Fellow at the Centre for the Development of Advanced Computing, focusing on embedded system design for space vehicle applications. Their experience also includes roles at Qualcomm, enhancing their expertise in ASIC/IP verification methodologies.