Anton Babundin

Anton Babundin is an accomplished ASIC/FPGA Design Verification Engineer with extensive experience in verifying image signal processing pipelines and developing test benches using SystemVerilog, UVM, and CocoTB. Currently at Artec 3D, Anton has created a CI/CD regression system for a full computer vision pipeline and worked with various industry-standard protocols such as AMBA and PCIe. Previous roles include positions at onsemi, where Anton focused on the verification and automation of hardware for Wi-Fi chips, and at the Skolkovo Institute of Science and Technology, where Anton developed peripheral blocks and conducted extensive testing using VHDL, Verilog, and Python. Anton holds a Master of Science degree in Radio-electronic systems and complexes from the Moscow Aviation Institute.