Bhavana Dhara

Bhavana Dhara is a highly skilled engineering professional with a strong background in Network on Chip (NoC) design and hardware development. Currently serving as a Staff NoC Solutions Architect at Arteris since February 2023, Bhavana previously held roles at Meta as a NoC Architect and at Qualcomm as a Senior Hardware Design Engineer, focusing on chip address mapping, microarchitecture, and high-performance NoCs. Early experiences include internships at Intel Corporation and Qualcomm, where responsibilities encompassed SoC design and physical design flow for 5G chipsets. Bhavana started a career as an Embedded Software Verification and Validation Engineer at UTC Aerospace Systems, contributing to firmware development for critical aerospace systems. Educational qualifications include a Master's degree in Electrical Engineering from the University of Southern California and a Bachelor of Engineering in Electronics and Communication Engineering from New Horizon College of Engineering.