Arteris
Bhavin Vaidya has a diverse work experience spanning over three decades. Bhavin started their career as a Customer Service Engineer at Pertec Computer Limited in 1985 before moving on to PSI Data Systems as a Senior Customer Service Engineer in 1987. At PSI Data Systems, they provided hardware and system support on various platforms.
In 1993, Bhavin joined Fujitsu ICIM Ltd. as a Senior Customer Service Engineer and Project Leader. Bhavin led projects for several prestigious organizations, including the Greater Bombay Police and British Deputy High Commission. Bhavin was responsible for site preparations, hardware and software installation, and network configuration.
In 1995, Bhavin transitioned to a Specialist role at Fujitsu ICIM Ltd., where they demonstrated expertise in system administration and hardware support. Bhavin worked on various server and workstation platforms, including SUN Sparc, HP 9000, IBM Power PC, and more.
From 1997 to 2001, Bhavin worked as a UNIX System Administrator consultant at Insight Solutions, where they provided support to Engineering and R&D teams at Cadence Design Systems. Bhavin resolved critical problems and conducted troubleshooting on various infrastructure issues.
Bhavin returned to Cadence Design Systems in 2001, joining as a Senior Unix Administrator. Bhavin contributed to the setup and rollout of server farm infrastructure, including LSF clusters and common tools. Over the years, Bhavin took on roles as an IT Architect and Senior IT Architect, focusing on managing large-scale clusters, implementing global common tools, and introducing new operating system images.
In 2016, Bhavin joined Arteris as an IT Lead, responsible for supporting Engineering and Field Service organizations. Bhavin'sduties included administering various tools and technologies, working with vendors and business partners, and managing compliance.
Throughout their career, Bhavin has showcased their abilities in system administration, hardware support, infrastructure management, and project leadership.
Bhavin Vaidya's education history began with their high school education at Smt. Gokalibai Punamchand Pitamber High School, which they completed in 1980. Bhavin then went on to pursue a Higher Secondary Certificate (HSC) in Science, specializing in Math, Physics, Chemistry, and Biology at Mithibai College of Arts Chauhan Institute of Science and A.J. College of Commerce and Economics from 1980 to 1982. Afterward, Bhavin attended The Maharaja Sayajirao University of Baroda, where they obtained a Diploma in Electrical Engineering from 1982 to 1985.
Additionally, Bhavin Vaidya has a certification in Platform LSF Advance Administrations, which they obtained from IBM Platform Computing in July 2011.
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Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.