Arteris
Mr. Janac is president and CEO of Arteris IP where he is responsible for growing and establishing a strong global presence for the company that is pioneering the concept of NoC technology. Charlie’s career spans 20 years and multiple industries including electronic design automation, semiconductor capital equipment, nano-technology, industrial polymers and venture capital.
In the first decade of his career, he held various marketing and sales positions at Cadence Design Systems (NASDAQ: CDNS) where he helped build it into one of the ten largest software companies in the world. He joined HLD Systems as president, shifting the company’s focus from consulting services to IC floor planning software and building the management, distribution and customer support organizations. He then formed Smart Machines, manufacturer of semiconductor automation equipment and sold it to Brooks Automation (NASDAQ: BRKS). After a year as Entrepreneur-in-Residence at Infinity Capital, a leading early-stage Venture Capital firm, where he consulted on Information Technology investment opportunities, he joined Nanomix as president and CEO helping build this start-up nano-technology company.
Mr. Janac holds a B.S. and M.S. degree in Organic Chemistry from Tufts University and an M.B.A from Stanford Graduate School of Business.
Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.