Kalu Chau

Director Of Revenue at Arteris

Kalu Chau, CPA has a strong background in revenue management and accounting. Kalu is currently employed at Arteris IP as the Director of Revenue, a position they assumed in October 2021. Prior to this, they worked at KLA as a Senior Revenue Manager from July to September 2021. From November 2017 to July 2021, Kalu held the role of Revenue Manager at KLA. Kalu served as the Revenue Accounting Manager at Silver Spring Networks from September 2015 to November 2017. Before that, Kalu worked as a Senior Financial Analyst - Revenue at Applied Materials from May 2011 to September 2015. Kalu began their career at PricewaterhouseCoopers as an Experienced Senior Assurance Associate from August 2006 to May 2011.

Kalu Chau, CPA, obtained a Master of Science degree in Applied Economics & Finance from the University of California, Santa Cruz from 2004 to 2006. Prior to that, they completed a Bachelor's degree in Business Management Economics at the same university from 2001 to 2005. In addition to their academic achievements, Kalu Chau has obtained the Certified Public Accountant (CPA) designation from the California Board of Accountancy. The specific month and year of obtaining this certification are not provided.

Location

Saratoga, United States

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Arteris

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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.


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201-500

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