Arteris
Richard Weber has a diverse work experience that spans over several decades. Richard started their career at Silicon Graphics as an MTS, where they worked from 1992 to 1997. Richard then joined StratumOne as a Principal Engineer from 1998 to 1999. Richard then moved on to Cisco Systems, where they held the position of Technical Leader for six years from 1999 to 2005.
In 2006, Richard became the CEO of Semifore, Inc. and held this position until 2022. During their time at Semifore, they played a vital role in the company's success.
In addition to their CEO role, Richard also actively participated in various IEEE Standards Association committees. Richard served as a Committee Member for the IEEE P1685 IP-XACT standard from 2009 to 2021. Richard's expertise in hardware software interface domain-specific languages proved invaluable, and they provided implementation in the Semifore CSRCompiler to verify standards before publication.
From 2007 to 2009, Richard served as a Committee Member for the Spirit Consortium SystemRDL Committee, where they showcased their expertise in SystemRDL and hardware software interface domain-specific languages. Richard provided reference implementation in the Semifore CSRCompiler to ensure the standard's accuracy before publication.
Richard also contributed to the Accellera Systems Initiative as a Committee Member. Richard specifically focused on the Accellera IP-XACT committee and Accellera UVM Committee. Richard'sexpertise in hardware software interface domain-specific languages allowed him to provide implementation and verification support for standards.
Currently, Richard works at Arteris as a Fellow and Director of Engineering. Richard started this role in January 2023, and their accomplishments in this position are yet to be determined.
Richard Weber attended the University of Illinois Urbana-Champaign, where they earned a Bachelor of Science (BS) degree in Computer Engineering from 1982 to 1985. Subsequently, they pursued further education at the same institution and obtained a Master of Science (MS) degree in Electrical Engineering from 1986 to 1987.
Arteris
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Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.