Arteris
Sarah Barousse has a strong background in engineering and application design, with experience at multiple companies. Sarah is currently working at Arteris IP as a Corporate Application Engineer, a role they have held since February 2021. Prior to this, they were an Application Design Manager at Arteris IP from September 2017 to April 2021. Sarah also held the same role from March 2016 to April 2021.
Before joining Arteris IP, Sarah worked as a Senior Design Engineer at FREESCALE SEMICONDUCTEURS FRANCE SAS from May 2015 to February 2016. Sarah was a Verification Engineer at Bull-Amesys conseil from January 2013 to May 2015. Sarah also worked as a Design Engineer at EASII-IC from October 2010 to January 2013 and at Sonics, Inc. from January 2010 to November 2010.
Sarah's earlier experience includes working as an HW Engineer at ALTRAN - TEXAS INSTRUMENTS from September 2006 to July 2009. At Texas Instruments, they worked as a System intern Engineer, focusing on SystemC modeling and coding, from March 2006 to September 2006. Sarah also worked as a System intern Engineer, specializing in coding and monitoring, from April 2005 to August 2005.
Sarah Barousse attended ESIEE Paris from 2001 to 2006. No specific degree or field of study was mentioned.
This person is not in any offices
Arteris
2 followers
Arteris is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world’s most important and sophisticated systems-on-chip(SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world’s first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements.ARTERIS IP PRODUCTS AND SOLUTIONSOur on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC® Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore® Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm®-based processor IP with other cache-coherent and non-coherent IP.The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache® Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed.To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products.Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO® Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.