Marco Pausini

Marco Pausini is an experienced FPGA SoC Engineer currently employed at AST SpaceMobile, where responsibility includes the design and verification of signal processing algorithms on Versal ACAP devices for space-based cellular broadband connectivity. Previously, at MetaSensing BV, Marco served as Principal FPGA Engineer, specializing in the architecture of digital units for satellite SAR imaging systems and leading radar baseband processor module development. Additional experience includes roles as an ASIC RTL Engineer at Barcelona Supercomputing Center, Principal Physical Layer Engineer at Xingtera, and positions at Keysight Technologies, Verigy, and a start-up company 3UB, focusing on various aspects of wireless communications and signal processing. Marco holds a Ph.D. in Wireless Communications from Delft University of Technology, along with degrees from CEFRIEL, Technische Universität Wien, and Alma Mater Studiorum – Università di Bologna.