Yt Lai

YT Lai is a Principal Engineer at ASTRI, with extensive experience in high precision oscillator design and transceiver system development. Notable projects include the design of a 14-bit DCXO for NBIoT, a +/-0.3ppm 14-bit DC-TCXO for NBIoT/GPS, and support for mass production within high-speed high-resolution DACs. Previous roles include Staff Design Engineer at Pericom Semiconductor, specializing in VC-TCXO design, Senior Analog Designer at ASTRI with a focus on CCD and gsensor analog front end systems, and Analog/RF IC Designer at Sirific Wireless, working on transmitter design for multiple generations of mobile technology. YT Lai holds a Master’s degree in Electrical Engineering from the University of Waterloo and a Bachelor’s degree in Electrical Engineering from the University of Alberta.