Chilai Huang

Mr. Huang got his Ph. D. in 1982. He has been working on the EDA business since then. He was the co-founder of Dr. Prabhu Goel of Gateway Design Automation, Inc. He and Mr. Phil Moorby worked on the language definition and first implementation of Verilog. Since then, he has been working in fault simulation, timing verification, and synthesis areas. He was responsible for Cadence’s RTL synthesis effort for several years and eventually led the whole synthesis project. He left Cadence and started Avery in 1998.