Vasudevan Devaraj is a Senior Lead RTL Design Engineer with over 8 years of experience in ASIC Digital Design, specializing in AMBA protocols such as AXI and CHI Bridge. Currently, they work at BITSILICA as an ASIC RTL Design Engineer after holding positions at Synopsys Inc and completing an internship at SmartDV Technologies India Private Limited. Vasudevan earned a Bachelor of Engineering in Electronics and Communications Engineering from the Coimbatore Institute of Engineering and Technology in 2016.
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