Jade Kizer is an experienced Chiplet IO Design Architect at Broadcom since August 2008, with a robust background in high-speed mixed-signal circuit design. Prior experience includes serving as a Circuit Designer at Avago Technologies from September 2008 to January 2016, where responsibilities involved technical leadership in the development of 20Gbps+ receiver SerDes designs. As a Principal Engineer at Rambus from June 2000 to July 2008, contributions were made to high-speed mixed-signal circuit design. Educational qualifications include a Master of Science in Electrical Engineering from Stanford University and a Bachelor of Science in Electrical Engineering from the South Dakota School of Mines. Additionally, Jade Kizer served in the US Army National Guard from July 1992 to May 2000, holding roles as SGT and SPC.
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