Yang Wang is an experienced engineer specializing in analog and mixed-signal circuit design. Currently employed at Broadcom as an Analog IC Design Engineer since May 2023, Yang focuses on electrical and optical transceiver technologies. Prior experience includes serving as a Senior Staff Analog IC Design Engineer at Marvell Technology, where Yang worked on high-speed SerDes circuit design from March 2022 to May 2023, and as a Senior Analog and Mixed-Signal Design Engineer at Synopsys Inc., responsible for system-level and architecture design for high-speed SerDes IPs ranging from 16Gb/s to 112Gb/s between January 2019 and March 2022. Yang Wang holds a Master's degree in Analog/mixed-signal circuits design from Peking University and is a PhD candidate at the University of Toronto, focusing on the same field of study.
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