Cv Ramana

CV Ramana is an accomplished engineering professional with extensive experience in design and management within the semiconductor industry. Currently serving as Design Engineering Director at Cadence Design Systems since August 2022, CV Ramana previously held the position of IP Design Manager at Intel from February 2008 to July 2022. Prior to that, CV Ramana was a Senior Design Engineer at LSI, an Avago Technologies Company, from April 2005 to January 2008, and began a career as a Design Engineer at United Microelectronics Solutions from August 2004 to March 2005. CV Ramana holds a Master of Technology (M.Tech.) in Electrical and Electronics Engineering from the Indian Institute of Technology, Kharagpur, and a Bachelor of Technology (BTech) in Electrical, Electronics and Communications Engineering from Jawaharlal Nehru Technological University.