Sankeerth Mamidala

Sankeerth Mamidala is a Solutions Engineer in Static Timing Analysis (STA) at Cadence Design Systems, a role held since July 2024. Prior to this position, Sankeerth worked as an STA Engineer at Apex Semiconductor from January 2022 to July 2024. Earlier experience includes a project internship at the Defence Research and Development Organisation (DRDO) from December 2020 to July 2021 and an internship at Entuple Technologies Pvt. Ltd. in June 2020. Sankeerth completed a Bachelor of Technology degree in Electronics and Communications, specializing in VLSI Design, from VIT Vellore Institute of Technology in 2021.