Sowmya Venkateswaran

Sowmya Venkateswaran is an experienced engineering professional with a strong background in design engineering and testability across various companies in the semiconductor industry. Currently serving as a Design Engineering Manager at Cadence Design Systems since September 2021, previous roles include Manager of Synthesis, STA, and DFT at Microchip Technology Inc. and earlier positions at Microsemi Corporation and PMC-Sierra. Sowmya's expertise encompasses full chip synthesis, static timing analysis (STA), design for testability (DFT), and automation through TCL scripting. Educational qualifications include a Master’s degree in Electrical Engineering from the University of Southern California and a Bachelor’s degree in Electronics and Communication Engineering from Anna University Chennai.