Steve Wells

Steve Wells is an experienced engineer in the field of VLSI design and ASIC development, currently serving as a DDR Design and Integration Engineer at Cadence Design Systems since November 2017. Previous positions include ASIC Design Engineer at Broadcom Limited, where expertise in high-speed networking ASIC design was developed, and roles at PHF, LLC as Director of Operations, Intel as a VLSI Design Engineer specializing in senior CPU design for the Montecito, Montvale, and Tukwila projects, as well as at Hewlett-Packard, contributing to the design of PA-RISC and Itanium processors. Steve Wells holds a Bachelor of Science in Electrical Engineering with a Computer Concentration from Colorado State University.