Bastien Giraud

Bastien Giraud is an experienced Memory Design Research Engineer at CEA since April 2010, specializing in low power digital and SRAM circuit design using BULK and fully depleted SOI technology at the 28nm and 14nm nodes. Key achievements include the study and design of innovative FDSOI device architectures, the porting of industrial design platforms from BULK to FDSOI, and extensive characterization of SRAM memory and standard cells. Giraud has also collaborated with STMicroelectronics and IBM, holding 15 strategic patents in memory design, while previously serving as a Post Doctoral Researcher at UC Berkeley, focusing on SRAM and digital IC design in 45nm CMOS technology, and as a PhD student at Télécom ParisTech investigating SRAM memory in Double Gate FD-SOI technology. Giraud's academic credentials include a PhD in memory IC design from Télécom Paris and a Master's degree in microelectronics IC design from Polytech Marseille.