Vignesh U is an experienced VLSI Project Engineer at Tech Mahindra Cerium Pvt Ltd since September 2021, specializing in TestChip Verification, IP and Subsystem Validation, and Test Bench Development, with expertise in gate-level simulations and functional coverage modeling using languages such as Python and Perl. Previous experience includes an Associate Engineer role at Brevera Technologies where Vignesh developed an automated testing design for PCB boards and an internship at Decibels Lab focusing on simulation models for electric vehicles. Vignesh holds a Bachelor of Engineering degree in Electrical and Electronics Engineering from St Joseph Engineering College and completed earlier qualifications at Canara College and Sri Narayana Guru School.
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