Vahid Amoozegar

Vahid Amoozegar is a skilled FPGA Engineer and Hardware Designer currently working at CERN since September 2017, where responsibilities include developing signal processing algorithms and controlling complex state machines using VHDL and Verilog. With additional expertise in designing interfaces such as PCIe Gen 2 and Gigabit Ethernet, as well as serial interfaces like SPI, I2C, and UART, Vahid has a strong background in embedded development, having previously worked on the Petalinux operating system for Xilinx Zynq FPGAs. Prior experience includes a role as an FPGA Engineer at Mehr Sanat Robotic, where multiple IP cores were designed and functionalities verified through SystemVerilog test benches, alongside work as a Hardware Designer focused on high-quality PCB layouts. Vahid holds a Master’s degree in Nuclear Electronics from Sharif University of Technology and a Bachelor's degree in Electrical and Electronics Engineering from Shahid Sattari Aviation University.