Farhad Andalibi

Farhad Andalibi is a Senior ASIC Verification Engineer at Ciena, where they previously held roles as a Junior and Intermediate ASIC Verification Engineer. They hold a Master of Applied Science in Electrical and Computer Engineering from Carleton University and a Bachelor of Science in Electrical and Electronics Engineering from Islamic Azad University. Farhad's expertise includes image processing, algorithm development, and real-time embedded system design using C++. They also have hands-on experience in testbench development and verification environments, utilizing Google Test, SystemVerilog, and UVM methodology. Prior to their current role, Farhad worked as a Research Assistant and Teaching Assistant at Carleton University and gained experience as an engineer intern and IT specialist at other organizations.