Katherine Kowalski

Katherine Kowalski is a Senior MTS (ASIC Design Verification Engineer) at Cerebras Systems since February 2021, following experience as a Design Verification Engineer. Previous positions include course assistant for Vector Calculus for Engineers at Stanford University, where Katherine facilitated review sessions on advanced mathematical concepts. Educational background includes Bachelor's and Master's degrees in Electrical, Electronics, and Communications Engineering from Stanford University. Internships at notable companies such as NVIDIA, IBM Research, and Northrop Grumman provided Katherine with hands-on experience in hardware verification, research in signal processing, and systems engineering. Further academic involvement includes contributions to machine learning research related to crystal data mapping at Stanford. Skills encompass programming in C, Perl, and Verilog, along with proficiency in FPGA implementation and digital system design.