Matthias Steidl is an experienced engineer with a strong background in electronic design and architecture, currently serving as an ASIC Architect at Ciena since August 2025. Matthias has held several significant positions, including Principal Engineer and SoC Architect at Coherent Corp. from November 2019 to July 2025, and Sr. Design Engineer at Intel from July 2007 to July 2014, focusing on microprocessor architecture and emulation technology research. Prior experience includes roles as Technical Marketing Engineer at both Socionext Europe and Fujitsu Semiconductor Europe, and Design Engineer at Freescale, where automotive SoC integration was a primary focus. Matthias completed a Master’s degree in Electrical Engineering with a specialization in Microelectronics from Technische Universität Dresden and a Bachelor’s degree in Electrical Engineering from Technische Universität Darmstadt.
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