Niankun Rao

Niankun Rao is a Senior ASIC/FPGA Engineer at Ciena since April 2022, previously serving as Development Lead Engineer at Schweitzer Engineering Laboratories from February 2012 to April 2022. In this role, Niankun led a multi-million-dollar project, managing over 10 engineers, and was responsible for system-level specifications, architectural solutions for FPGA and firmware, project scheduling, and budget estimates. Niankun's extensive experience includes roles as Lead Hardware Engineer, Hardware Engineer, Firmware Engineer, and Verification Engineer at SEL, involving complex circuit design, firmware development, and test automation using various programming languages and tools. With a Master of Applied Science in Mechanical Engineering from The University of British Columbia and a Bachelor of Engineering (Honors) in Electrical Engineering from Harbin Institute of Technology, Niankun has a strong educational background complemented by practical research experience as a Research Assistant at UBC.