SG

Sheida Gohardehi

Senior Digital ASIC Design Engineer

Sheida Gohardehi, Ph.D., is an accomplished digital design and hardware engineer with over 6 years of experience in VLSI and low-power digital circuit design. Currently, they serve as a Senior Digital ASIC Design Engineer at Ciena and a Post Doctoral Fellow at the University of Waterloo, focusing on low-power circuits for portable display applications. Previously, they held positions as a Research Associate, where they worked on pixel circuit design and display drivers, and as a Research Assistant at the University of Tehran, specializing in RTL design with VHDL and Verilog. Sheida possesses extensive skills in FPGA programming, ASIC design, and display technology.

Location

Ottawa, Canada

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