Ankur Baijal

Ankur Baijal is a seasoned technical professional with extensive experience in hardware engineering and verification. Currently serving as a Technical Lead at Cisco since April 2010, Ankur Baijal develops a complete emulation platform for next-generation ASICs and manages testbench development using SystemC, C++, Verilog, and SystemVerilog. Prior to this role, Ankur Baijal worked as a Hardware Engineer at Cisco, where responsibilities included chip verification and the development of a comprehensive verification environment utilizing SystemVerilog/UVM. Ankur Baijal's career also includes positions at Aprius as a Verification Consultant, at IDT as a System Verification Engineer, at GDA Technologies as a Hardware Engineer, and as an Intern Application Engineer at QuickLogic. Ankur Baijal holds a Bachelor's degree in Electronics from Savitribai Phule Pune University and furthered education with studies at San Jose State University.