Ayan R

Ayan R is an experienced ASIC Engineering Technical Leader at Cisco, with a career beginning in physical design engineering. Previously held positions include Senior Staff Physical Design Engineer and Staff Physical Design at Synopsys Inc, and Senior Staff Engineer, Staff Engineer, and Technical Lead at STMicroelectronics. Ayan R's earlier experience features a role as an Engineer at SmartPlay Technologies, consulting for Qualcomm. Ayan R's expertise encompasses design compiler topographical flow, UPF-based synthesis, placement optimization, routing congestion analysis, and static timing analysis. Academically, Ayan R holds a Bachelor of Technology in Electronics and Communications Engineering from Heritage Institute of Technology, a Master of Science in In-memory Computing from the Indian Institute of Technology, Delhi, and a certification in Leadership with AI from the Indian School of Business.