GANG LI

Gang Li is an ASIC Engineering Technical Leader at Cisco, where they currently focus on semiconductor packaging process and reliability qualification. They have a robust background in failure analysis and reliability impacts associated with various packaging techniques. Previously, Gang held positions as a Senior FA Engineer and Senior Package R&D Engineer at Intel Corporation. They completed a PhD in Mechanical Engineering at North Carolina State University and earned both a Master's and Bachelor's degree from Nanjing University of Aeronautics and Astronautics. Throughout their career, Gang has demonstrated expertise in data analysis, scripting, and collaboration with manufacturing teams and suppliers.