Pradheep G

Pradheep G is an ASIC Engineering Technical Leader with over 14 years of experience in Physical Design Engineering and Application Engineering. They specialize in Place-and-Route for advanced technology nodes, including FinFET 3nm to 16nm, and have demonstrated expertise across Mobile, Automotive, Networking, and Wireless segments. Currently, at Cisco, Pradheep leads ASIC engineering efforts, while past roles at Cadence, Synopsys, and various design houses involved significant contributions to complex chip designs and physical verification processes. Pradheep is proficient in Cadence and Synopsys tools, guiding teams in delivering high-quality designs on schedule.