Fedor Borisovskii

Fedor Borisovskii has been working in the field of hardware design engineering since 2010. Fedor began their career as a Research Scientist at the Saint-Petersburg State University of Aerospace Instrumentation, where they conducted research on DSP algorithms implementation techniques in FPGA and ASIC RTL. Fedor also researched modern ECC decoders, such as BCJR decoder for turbo codes, Viterbi decoder for convolutional codes, and BP decoder for LDPC codes. In 2013, they moved to ICT academy SPB as a Hardware Design Engineer, where they implemented FPGA RTL of DSP algorithms, as well as JPEG2000 encoder FPGA implementation (CDF 9/7 FHD 30fps). In 2015, they joined CloudBEAR as a Senior Hardware Design Engineer, where they worked on RTL RISC-V implementation, execution pipeline, FPU, and debug module, as well as out-of-order and multiple instructions fetch decode and issue verification.

Fedor Borisovskii attended Saint Petersburg State University of Aerospace and Instrumentation from 2007 to 2012, earning a degree in Instrumentation Specialization in Aerospace Systems/Control and Information Systems.