Xiang Li

Xiang Li is a senior digital system engineer at CSIRO, specializing in RTL design, functional verification, and FPGA design, with extensive experience in Verilog, VHDL, SystemVerilog, and UVM. Previously, they held various engineering positions, including senior Xilinx field application engineer at 世健系统 and digital ASIC design engineer roles at companies such as Qualcomm and Movandi. Xiang holds a Master’s degree in Computing and Engineering from The Australian National University and a Bachelor's degree in Electronics Information Engineering from Southern Yangtze University.