Purushothama K M

Purushothama K M is a dedicated RTL Design Engineer currently working at Cyient. Previously, they held the position of Junior RTL Design Engineer at MeyvnSystems after completing a traineeship at Maven Silicon. Purushothama began their career in RTL design in February 2020 and holds a degree in Electronics from Visvesvaraya Technological University, which they earned in 2020. They possess strong technical skills in Verilog, Advanced Verilog, and Digital Electronics, complemented by effective communication and teamwork abilities.