Jaykant Timbadiya

Jaykant Timbadiya is a skilled engineer with extensive expertise in SoC design and micro-architecture. Current position as a Senior RTL Design Engineer at Google follows impactful roles including SoC Architect at Intel Corporation, where Jaykant defined architectures for RISC-V-based CPU subsystems. Prior experience includes serving as a Senior Engineer at Mindtree Limited, specializing in Bluetooth low energy IP design, and as a SOC Design Engineer at Intel India Private Limited, focusing on RTL and SoC design collaboration across various teams. Education includes a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Nirma University and a Master's Degree in VLSI Design from DAIICT Gandhinagar.