Nithesh Kurella

Nithesh Kurella has over 8 years of work experience in the fields of Machine Learning, System-on-Chip (SoC) Performance Architecture, and Computer Architecture. In 2022, they began working as a Principal ML Architect for d-Matrix. Prior to this, they were a SoC Performance Architect at AMD from 2019-2022. From 2015-2019, they were a Senior Performance Architect at Samsung Austin R&D Center, where they designed, modeled, and evaluated new features to improve CPU performance in a low power, high performance SMT enabled processor. Nithesh also modeled and evaluated several micro architectural features across Load Store and MMU blocks such as walk caches, area efficient load store schedulers, TLB organization, and identified and provided solutions for micro-architectural performance bottlenecks. Nithesh also worked as a Performance Architecture Intern for Samsung Austin R&D Center from 2015-2019. From 2013-2015, they were a Graduate Student Researcher, Graduate Teaching Assistant-Computer Systems Lab-II, and Graduate Teaching Assistant-Computer Architecture at the University of Massachusetts Amherst.

Nithesh Kurella completed a Bachelor of Engineering (B.E.) in Electrical, Electronics and Communications Engineering from BNM Institute of Technology between 2008 and 2012. Nithesh then went on to pursue a Master's degree in Computer Engineering at the University of Massachusetts Amherst, which they completed in 2015. Nithesh also attended SBMJC, but no further information is available.