Odysseus Adamides

Odysseus Adamides is a seasoned hardware engineering professional currently serving as the Hardware Engineering Manager at D3 since June 2018, where management of a diverse team of circuit designers, layout engineers, and FPGA engineers focuses on process improvement, training, and resource allocation. Previous roles at D3 include Hardware Engineer, responsible for designing and testing advanced electronic circuits, and Hardware Engineering Intern, working on hardware and firmware design. Odysseus gained additional experience with the RIT SAE Baja Team as a Data Acquisition Team Member, and held internships at TE Connectivity, Toyota Motor Corporation, and Toyota North America, contributing to various engineering projects. Odysseus’ educational background includes a Doctor of Philosophy, Master of Science, and Bachelor of Science in Electrical and Electronics Engineering from the Rochester Institute of Technology, with an expected PhD completion in May 2024.