Rohit Dhage is an accomplished engineering professional with extensive experience in FPGA design and application engineering. Currently serving as a Senior Researcher/FPGA Designer at DRW since May 2020, Rohit previously held the position of Senior Application Engineer for HAPS HW at Synopsys Inc from January 2017 to May 2020. Additional experience includes a role as a Silicon Design Engineer Intern at Microsoft in mid-2016, and as a Senior Design Engineer at Mobiveil from July 2013 to July 2015. Earlier in the career, Rohit worked as a Design Engineer II at Xilinx and as a Design Engineer at Mistral Solutions Pvt. Ltd. Rohit holds a Master of Science in Electrical Engineering from San José State University and a Bachelor of Technology in Electronics and Communications Engineering from Motilal Nehru National Institute Of Technology, along with foundational education from SKCH PU College and Jyothy Kendriya Vidyalaya.
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