Yuri Rozenfeld

Yuri Rozenfeld is an accomplished RFIC Engineer with extensive experience in the design and validation of RF and analog components. Currently at DSP Group since September 2021, Yuri has successfully designed an RF RX front-end for ULE applications utilizing TSMC's 22nm ULP process. Prior experience at Elipse from 2008 to 2021 includes designing various RFIC blocks such as LNAs, mixers, VCOs, power amplifiers, and high-speed operational amplifiers, along with guiding layout designs for optimal performance. Early career experience at Intel from 2005 to 2008 involved developing test programs and managing yield analysis for high-speed devices. Academic qualifications include a BSc in Electrical Engineering from the Technion - Israel Institute of Technology.