Kamaljit Dhooria

Kamaljit Dhooria is an experienced professional in design verification with a robust background in leading verification efforts for advanced ASICs and AI technologies. Currently serving as Director of Design Verification at Eridu AI since April 2025, Kamaljit previously worked at Juniper Networks from November 2019 to April 2025 as ASIC Verification Lead/Senior Manager, where responsibilities included leading the verification of front-end data path blocks for high-performance networking ASICs. Prior roles encompass Principal Engineer at NovuMind Inc., focused on verifying AI accelerator ASICs, Senior Staff at Qualcomm Inc., working on WIFI model PHY integration, and Validation Architect at Intel Corporation, responsible for USB 3.1 test plan development. Kamaljit holds a Master’s degree in Electrical Engineering from UNSW, Sydney, and a Bachelor’s degree in Electrical Engineering from the Indian Institute of Technology, Delhi.