Naresh S S

Naresh S S is a Senior Design Verification Engineer currently working at Excelmax Technologies in Bangalore, specializing in SOC verification for Samsung Semiconductor India Research. Naresh completed a Master of Technology in Digital Electronics and Advanced Communication at MIT, Manipal, and previously earned a Bachelor of Engineering in Electronics and Communication from PES Institute of Technology & Management. Naresh has extensive experience in IP verification through roles at Tessolve Semiconductor and Samsung Semiconductor India Research, and gained hands-on experience in FPGA design verification during an internship at GE Healthcare. Naresh's technical skills include proficiency in VHDL, Verilog, SystemVerilog, and various high-speed communication protocols.