Jixiang D. is a Senior ASIC Verification Engineer with experience at Synopsys Inc and Cisco. Jixiang completed a Master of Science in Electrical and Computer Engineering from the University of Michigan in 2022 and holds a Bachelor of Engineering from 四川大学, earned in 2020. They have held multiple roles in ASIC design verification, contributing significantly to their field. Currently, Jixiang is actively seeking a full-time position.
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