Ganesh Varma is an accomplished Senior RTL Design Engineer with extensive experience in the field of FPGA design and RTL engineering. Currently employed at Google, Ganesh previously held senior roles at Qualcomm and SmartSoC Solutions Pvt Ltd, and served as an FPGA Design Engineer at Saankhya Labs Pvt. Ltd. and Jiva Sciences Pvt. Ltd. Notable contributions include generating UPF, resolving VCLP violations, and implementing isolation, retention, and power switch controls in RTL using the TensorBuilder integration tool, as well as conducting power estimation using the JOULES Tool. Ganesh's educational background includes a Bachelor of Technology in Electronics and Communication from Aurora's Scientific Technological And Research Academy, completed in 2018.
This person is not in the org chart
This person is not in any teams
This person is not in any offices