Paresh Patel

Paresh Patel is an experienced engineer specializing in ASIC design and verification, with a career spanning over a decade. Starting as a Trainee at the Institute For Plasma Research in early 2009, Paresh transitioned to a role as Jr Engineer at Gujarat State Electricity Co Ltd in early 2010. Following this, Paresh held positions as an ASIC Engineer at E-infochips Pvt Ltd and as an ASIC Verification Engineer at AMD. From 2014 to 2019, Paresh worked as a Senior ASIC Verification Engineer at Synopsys India Pvt Ltd before moving to Qualcomm as a Senior Verification Engineer. After a brief period at Google as an ASIC Design Verification Engineer, Paresh continued to advance in the role, demonstrating expertise in verification processes. Currently, Paresh holds the position of ASIC Design Verification Engineer at Google, with a strong foundation in ASIC technologies and a focus on high-quality design verification.