Pooja Agarwal is a highly skilled engineer with extensive experience in the semiconductor and electronics fields. Currently serving as a Circuit Design Engineer at Google since October 2024, Pooja previously held the position of Staff Engineer at Samsung Foundry from October 2021 to October 2024. Pooja's professional background includes roles as a Memory Design Engineer at Arm and Exiger Technologies, along with a fruitful internship at the Defence Research and Development Organisation focused on modeling laser oscillators using MATLAB. Pooja's technical expertise encompasses SRAM/RF embedded memory compilers, with a strong focus on leakage characterization and analysis. Pooja holds a Master of Technology in Integrated Circuit Design from the Indian Institute of Technology, Delhi, as well as a Master of Science in Electronics from Delhi University, complemented by a Bachelor of Science with Honors in Electronics from Hansraj College.
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