Senthil S

Senthil S is a seasoned Front End IP & Sub-system Design Engineer/Manager with 17 years of experience in the VLSI industry. They have held significant roles at companies such as Google, Qualcomm, Intel, and Synopsys, focusing on CPU design, RTL design, and verification across multiple projects. Senthil’s expertise includes design specification development, timing closures, and formal property validation, showcasing a strong proficiency in various EDA tools. They earned a B. Tech in Electronics and Communication from the National Institute of Technology, Tiruchirappalli, and are currently pursuing a PGP in Artificial Intelligence & Machine Learning from The University of Texas at Austin.