Vincent Y.

Vincent Y. is currently a Kirin SoC System Architect, Team Leader, and Project Manager at Hisilicon, where they lead a team in designing and verifying the architecture of various chip components, including NoC and DDR controllers. Previously, they worked as a Staff SoC Design Engineer at Entropic Communications, focusing on ARM-based SoC design, and held positions as a Senior ASIC Design Engineer at Silicon Image and an ASIC Design Engineer at S3 Graphics, gaining extensive experience in chip design and verification processes. Vincent Y. holds a Master's degree in Microelectronics from Tsinghua University.